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M48T128Y M48T128V*
5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER(R) SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, AND CRYSTAL BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, AND SECONDS AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T128Y: VCC = 4.5 to 5.5V 4.1V VPFD 4.5V - M48T128V*: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS 10 YEARS OF DATA RETENTION AND CLOCK OPERATION IN THE ABSENCE OF POWER SELF-CONTAINED BATTERY AND CRYSTAL IN THE DIP PACKAGE PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs
Figure 1. 32-pin PMDIP Module
32 1
PMDIP32 (PM) Module
* Contact local ST sales office for availability of 3.3V version.
February 2005
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M48T128Y, M48T128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13.PMDIP32 - 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. PMDIP32 - 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 19 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M48T128Y, M48T128V*
SUMMARY DESCRIPTION
The M48T128Y/V TIMEKEEPER(R) RAM is a 128Kb x 8 non-volatile static RAM and real time clock. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. The M48T128Y/V directly replaces industry standard 128Kb x 8 SRAM. Figure 2. Logic Diagram
VCC
It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. Table 1. Signal Names
A0-A16 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Supply Voltage Ground Not Connected Internally
17 A0-A16 W E G M48T128Y M48T128V
8 DQ0-DQ7
E G W VCC VSS NC
VSS
AI02244
Figure 3. DIP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 3 30 4 29 28 5 27 6 7 26 8 M48T128Y 25 9 M48T128V 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI02245
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48T128Y, M48T128V*
Figure 4. Block Diagram
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8x8 TIMEKEEPER REGISTERS A0-A16
131,064 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
VSS
AI01804
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M48T128Y, M48T128V*
OPERATION MODES
Figure 4., page 5 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations consisting of BiPORTTM READ/WRITE memory cells within the static RAM array. The M48T128Y/V includes a clock control circuit which updates the clock bytes with current information once per secTable 2. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 4.5 to 5.5V or 3.0 to 3.6V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
ond. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T128Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER (R) Register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 11., page 18 for details.
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M48T128Y, M48T128V*
READ Mode The M48T128Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be availFigure 5. READ Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
able after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access.
VALID tAXQX tEHQZ
tGHQZ
Note: WE = High.
Table 3. READ Mode AC Characteristics
M48T128Y Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 5 70 70 70 40 5 5 30 30 -70 Max Min 85 85 85 55 M48T128V -85 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF.
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M48T128Y, M48T128V*
WRITE Mode The M48T128Y/V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02382
tWHAX
tWHQX
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI02383
tELEH
tEHAX
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M48T128Y, M48T128V*
Table 4. WRITE Mode AC Characteristics
M48T128Y Symbol Parameter
(1)
M48T128V -85 Unit Max ns ns ns ns ns ns ns ns ns ns ns 30 70 70 5 ns ns ns ns
-70 Min Max Min 85 0 0 60 65 5 15 35 35 5 15 25 60 60 5
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH tAVEH tWHQX(2,3)
WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable 1 High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
70 0 0 50 55 5 10 30 30 5 10
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48T128Y, M48T128V*
Data Retention Mode With valid VCC applied, the M48T128Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T128Y/V may respond to transient noise
spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T128Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max).
10/22
M48T128Y, M48T128V*
CLOCK OPERATIONS
Reading the Clock Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register (1FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' Setting the Clock Bit D7 of the Control Register (1FFF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the Table 5. Register Map
Data Address D7 1FFFFh 1FFFEh 1FFFDh 1FFFCh 1FFFBh 1FFFAh 1FFF9h 1FFF8h 0 0 0 0 0 ST W R D6 D5 D4 D3 D2 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration D1 D0 10 Years 0 0 FT 0 0 Function/Range BCD Format Year Month Date Day Hours Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 5., page 11). Resetting the WRITE Bit to a '0' then transfers the values of all time registers 1FFFFh-1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur one second later. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within 1FFF9h. Setting it to a '1' stops the oscillator. The M48T128Y/V is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T128Y/ V oscillator starts after one second.
10 Date 0 0
10 Hours 10 Minutes 10 Seconds S
Keys: S = SIGN Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' Z = '0' and are Read only Y = '1' or '0'
11/22
M48T128Y, M48T128V*
Calibrating the Clock The M48T128Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 8., page 13). The M48T128Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in Figure 9., page 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is load-
ed, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. One method is available for ascertaining how much calibration a given M48T128Y/V may require. This involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in the STMicroelectronics Application Note, "TIMEKEEPER CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. For example, a deviation of 21 seconds slow over a period of 30 days would indicate a -8 ppm oscillator frequency error, requiring a +2(WR100010) to be loaded into the Calibration Byte for correction.
12/22
M48T128Y, M48T128V*
Figure 8. Crystal Accuracy Across Temperature
ppm 20
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 9. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
13/22
M48T128Y, M48T128V*
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 10) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
14/22
M48T128Y, M48T128V*
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 6. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages M48T128Y Supply Voltage M48T128V Output Current Power Dissipation -0.3 to 4.6 20 1 mA W Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 Unit C C C V V
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). No preheat above 150C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
15/22
M48T128Y, M48T128V*
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48T128Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T128V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC Testing Load Circuit
DEVICE UNDER TEST
650
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
Note: 50pF for M48T128V.
Table 8. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 20 20 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
16/22
M48T128Y, M48T128V*
Table 9. DC Characteristics
M48T128Y Symbol Parameter Test Condition
(1)
M48T128V -85 Unit Max 2 2 50 4 3 -0.3 2.2 0.4 VCC + 0.3 0.4 2.2 A A mA mA mA V V V V
-70 Min Max 2 2 95 8 4 -0.3 2.2 0.8 VCC + 0.3 0.4 2.4 Min
ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V
IOL = 2.1mA IOH = -1mA
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
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M48T128Y, M48T128V*
Figure 12. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSS tF tDR tREC tFB INPUTS
RECOGNIZED
tRB DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI03612
Table 10. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tREC Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to Inputs Recognized Min 300 10 0 1 40 200 Max Unit s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol VPFD Parameter(1,2) M48T128Y Power-fail Deselect Voltage M48T128V M48T128Y VSO tDR(3) Battery Back-up Switchover Voltage M48T128V Expected Data Retention Time 10 VPFD -100mV V YEARS 2.7 2.9 3.0 3.0 V V Min 4.1 Typ 4.35 Max 4.5 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 3. At 25C; VCC = 0V.
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M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION
Figure 13. PMDIP32 - 32-pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 12. PMDIP32 - 32-pin Plastic Module DIP, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
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M48T128Y, M48T128V*
PART NUMBERING
Table 13. Ordering Information Scheme
Example: M48T 128Y -70 PM 1 TR
Device Type M48T
Supply Voltage and Write Protect Voltage 128Y = VCC = 4.5 to 5.5V; VPFD = 4.1 to 4.5V 128V(1) = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed -70 = 70ns (128Y) -85 = 85ns (128V)
Package PM = PMDIP32
Temperature Range 1 = 0 to 70C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. Contact local ST sales office for availability of 3.3V version.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
20/22
M48T128Y, M48T128V*
REVISION HISTORY
Table 14. Document Revision History
Date June 1998 01/31/00 03/30/00 07/20/01 09/21/01 05/23/02 08/07/02 28-Mar-03 06-Aug-04 22-Feb-05 Version 1.0 1.1 1.2 2.0 2.1 2.2 2.3 3.0 4.0 5.0 First Issue Calibrating The Clock Paragraph changed Storage Temperature changed (Table 6) Reformatted; temperature information added to tables (Table 8, 9, 3, 4, 10, 11) Corrected speed grade in ordering information Add countries to disclaimer; add marketing status Refine marketing status text v2.2 template applied; test condition updated (Table 11) Reformatted; updated Register Map (Table 5) IR reflow update (Table 6) Revision Details
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M48T128Y, M48T128V*
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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